1. Field of the Invention
The present invention relates to semiconductor memory devices and, in particular, to nonvolatile semiconductor memory devices for storing data in a nonvolatile fashion. More specifically, the invention relates to a nonvolatile semiconductor memory device superior in area use efficiency.
2. Description of the Background Art
As one type of semiconductor memory devices, there is a nonvolatile semiconductor memory device that retains data in a nonvolatile fashion. One typical example of the nonvolatile semiconductor memory devices is flash EEPROM (electrically erasable programmable read-only memory, hereinafter referred to as flash memory) capable of electrically programming (writing) and erasing data.
FIG. 12 schematically shows an exemplary structure of a memory cell of a conventional flash memory. Referring to FIG. 12, the memory cell includes impurity regions SR and DR formed, being spaced apart from each other, on a substrate region SUB, a floating gate FG formed above the region between impurity regions SR and DR with an insulating film (not shown) laid thereunder, and a control gate CG placed above and facing floating gate FG.
Impurity regions SR and DR serve as source and drain regions, respectively. This nonvolatile memory cell is constituted of a stacked gate field effect transistor having the control gate and floating gate. The nonvolatile memory cell has a threshold voltage changed according to the amount of charges (electrons) accumulated on floating gate FG, and stores data according to whether or not the threshold voltage is higher than a reference voltage.
The operations of injection of charges into floating gate FG and ejection of charges out of floating gate FG are referred to differently depending on the configuration of peripheral circuitry of the flash memory cell. For one nonvolatile semiconductor memory device, the state in which charges are drawn out of floating gate FG is referred to as a written state (programmed state) while the state in which charges are injected into floating gate FG is referred to as an erased state. For another nonvolatile semiconductor memory device, the state in which charges are drawn out of floating gate FG is referred to as the erased state while the state in which charges are injected into floating gate FG is referred to as the written (programmed) state.
Regardless of the memory cell structure, data is stored according to the amount of charges accumulated on the floating gate.
FIG. 13 schematically shows a distribution of data stored in nonvolatile memory cells. In FIG. 13, the vertical axis represents threshold voltage Vth of the nonvolatile memory cells and the horizontal axis represents the number of memory cells (bits).
It is supposed here that semiconductor substrate region SUB is a p-type substrate region and a nonvolatile memory cell is constituted of an n-channel field effect transistor. Thus, increase in the number of electrons accumulated on floating gate FG increases threshold voltage Vth. According to the amount of charges accumulated on floating gate FG, the region where threshold voltages Vth of the memory cells distribute is divided into region RA and region RB. In region RA, threshold voltage Vth is higher than reference voltage VREF. In region RB, threshold voltage Vth is lower than reference voltage VREF. Depending on whether a nonvolatile memory cell falls in region RA or region RB, the memory cell can store data of a different logic level.
For example, whether the nonvolatile memory cell falls in region RA or RB can be determined according to whether or not a current flows between impurity regions SR and DR of the nonvolatile memory cell when reference voltage VREF is applied to control gate CG. Specifically, if the nonvolatile memory cell falls in region RA, reference voltage VREF applied to control gate CG does not cause a channel to be formed therein and accordingly causes no current to flow between impurity regions SR and DR. On the other hand, if the nonvolatile memory cell falls in region RB, in accordance with reference voltage VREF applied to control gate CG, a channel is formed between impurity regions SR and DR and accordingly a current flows in between.
In other words, the nonvolatile memory cell stores data of different logic levels, i.e., binary data of a single bit, according to whether the threshold voltage of the memory cell is higher or lower than reference voltage VREF.
FIG. 14 shows another distribution of data stored in memory cells. Referring to FIG. 14, the region where threshold voltages Vth of the memory cells distribute is divided into four regions RG0-RG3 based on reference voltages VREF1-VREF3. Different data is stored depending on where threshold voltage Vth of a nonvolatile memory cell falls among regions RG0-RG3. According to the threshold voltage distribution as shown in FIG. 14, the nonvolatile memory cell can assume one of the four states. When regions RG0-RG3 are correlated with data xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c3xe2x80x9d, for example, this nonvolatile memory cell can thus store four-level data. This means that the nonvolatile semiconductor memory device having the threshold voltage distribution as shown in FIG. 14 can store two-bit data per cell.
If a single memory cell stores multilevel data, such as four-level data, this storage of multi-bit data per cell allows reduction in the number of memory cells, as compared with the construction for storage of binary data per cell. Consequently, the area occupied by a memory array can be reduced. However, writing/reading of multilevel data requires comparison between each of three stepped reference voltages VREF1-VREF3 with threshold voltage Vth of this memory cell. Therefore, for storage or reading of data, the voltage to be applied to control gate CG has to be changed in three steps. Consequently, the nonvolatile memory cell storing the multilevel data (hereinafter referred to as multilevel mode memory cell) requires a longer time to write and read data, as compared with the nonvolatile memory cell storing binary data (hereinafter referred to as binary mode memory cell), which results in a longer access time.
Japanese Patent Laying-Open Nos. 2001-6374 and 11-345491 for example disclose a configuration intended for improving data reliability and reducing the area occupied by a memory array, in which multilevel mode memory cells and binary mode memory cells are formed in the common memory array.
According to the above-mentioned prior art, multilevel mode memory cells and binary mode memory cells are formed within the same memory array and these memory cells are fabricated under the same manufacturing conditions. It is accordingly impossible to make transistor characteristics required for binary mode memory cells different from transistor characteristics required for multilevel mode memory cells. A problem is caused that the reliability of both binary mode and multilevel mode memory cells is difficult to ensure.
In general, the multilevel mode memory cells are formed intending to replace a hard disk as an application. The multilevel mode memory cells are required, according to the specification thereof, to allow a greater number of times of rewriting, as compared with the binary mode memory cells. Therefore, for data writing, the number of times programming and erasure pulses are applied to the multilevel mode memory cells as well as the time consumed for this pulse application are increased beyond those of binary mode memory cells. For writing of data, a greater voltage stress is accordingly applied to gate insulating films (or tunnel insulating films) of the multilevel mode nonvolatile memory cells than that in the binary mode memory cells. Therefore, when the multilevel mode memory cells and binary mode memory cells are fabricated under the same manufacturing conditions a problem of degradation in the reliability of stored data is caused as the multilevel mode memory cells are rewritten an increased number of times.
If the characteristics of the binary mode memory cells are adapted to those of the multilevel mode memory cells, an excessively higher reliability is required for the gate insulating film of the binary mode memory cells. Therefore, the thickness of the gate insulating film is increased, which disadvantageously increases an access time of the binary mode memory cells.
In addition, the amount of transported charges in one writing/erasing operation of a binary mode memory cell is different from that of a multilevel mode memory cell. Further, in reading, a voltage applied to a selected word line (control gate) is different between the binary mode memory cell and the multilevel mode memory cell. Therefore, if the common control circuit is used for access control of the multilevel mode memory cell and of the binary mode memory cell, a significant burden would be loaded on the control circuit.
As for the multilevel memory cells, in order to implement the same storage capacity, a required number of memory cells is smaller than that of binary mode memory cells. Thus, the area occupied by the array of multilevel mode memory cells can be made smaller than that of binary mode memory cells. However, for the array configuration including multilevel mode memory cells, if fusible link elements (fuse elements) are used for repairing of a defective address, internal voltage trimming and such, the link elements each occupy a relatively larger area than the area occupied by memory cell transistors. This is done for preventing any adverse effect, such as the short circuit in an element located near the link elements, due to scattering of the fragment of a blown off link element. Therefore, where a program circuit constituted of such fuse elements is used, the program circuit requires a large layout area and thus makes it impossible to reduce the chip area, which would provide a great drawback to the reduced chip area that is one advantage of the multilevel mode memory.
An object of the present invention is to provide a highly reliable nonvolatile semiconductor memory device occupying a small area and capable of surely storing data.
Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of surely storing binary data and multilevel data depending on an application of use, without deteriorating a system performance.
Still another object of the present invention is to provide a nonvolatile semiconductor memory device occupying a small area and capable of surely storing data for setting an internal state.
A semiconductor memory device according to an aspect of the present invention includes a first memory array having a plurality of first memory cells each storing single-bit data and a second memory array having a plurality of second memory cells each storing multi-bit data. The first and second memory arrays are formed in separate regions. The first memory array and the second memory array have respective address spaces fixedly allocated in advance. The address spaces are made non-overlapping with each other for the first and second memory arrays. The first and second memory arrays are formed on a common semiconductor substrate.
A nonvolatile semiconductor memory device according to another aspect of the present invention includes a first memory array having first memory cells each storing multi-bit information, and a program circuit for storing information for setting a predetermined internal state. The first memory array and the program circuit are formed in separate regions. The program circuit includes a memory cell which is the same in structure as a memory cell storing single-bit data.
A first memory array having binary mode memory cells and a memory array having multilevel mode memory cells are formed in separate regions. Therefore, optimized memory cells can be manufactured in the first and second memory arrays. A highly reliable semiconductor memory device occupying a small area is implemented.
The information for setting a predetermined internal state is stored by the memory cell having the same structure as that of the first memory cell, and the binary data can be stored in a stable and accurate state and accordingly, the internal state can stably be maintained in the programmed state.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.